Integrated complementary graphene inverter

The operation of a digital logic inverter consisting of one p- and one n-type graphene transistor integrated on the same sheet of monolayer graphene is demonstrated. The type of one of the transistors was inverted by moving its Dirac point to lower gate voltages via selective electrical annealing. Boolean inversion is obtained by operating the transistors between their Dirac points. The fabricated inverter represents an important step towards the development of digital integrated circuits on graphene.Comment: 4 pages, 4 figure

Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technologyComment: to appear in IEEE Transactions on Electron Devices (2014

Controlling the threshold voltage of a semiconductor field-effect transistor by gating its graphene gate

The threshold voltage of a field-effect transistor (FED determines its switching and limits the scaling of the supply voltage in the logic gates. Here we demonstrate a GaAs FET with a monolayer graphene gate in which the threshold voltage was externally controlled by an additional control gate. The graphene gate forms a Schottky junction with the transistor channel, modulating the channel conductivity. The control gate sets the work function of the graphene gate, controlling the Schottky barrier height and therefore the threshold voltage, and reduces the subthreshold swing down to similar to 60 mV dec(-1). The change of the threshold voltage was large enough to turn the initially depletion mode FETs into the enhancement mode FETs. This allowed to realize logic gates with a positive switching threshold in which the threshold voltage of each transistor was independently set. The presented FETs can also be operated as dual-gate FETs, which was demonstrated by realizing frequency mixers

Suspended monolayer graphene under true uniaxial deformation

2D crystals, such as graphene, exhibit the higher strength and stiffness of any other known man-made or natural material. So far, this assertion has been primarily based on modelling predictions and on bending experiments in combination with pertinent modelling. True uniaxial loading of suspended graphene is not easy to accomplish; however such an experiment is of paramount importance in order to assess the intrinsic properties of graphene without the influence of an underlying substrate. In this work we report on uniaxial tension of graphene up to moderate strains of 0.8% ca.. This has been made possible by sandwiching the graphene flake between two polymethylmethacrylate (PMMA) layers and by suspending its central part by the removal of a section of PMMA with e-beam lithography. True uniaxial deformation is confirmed by the measured large phonon shifts with strain by Raman spectroscopy and the indication of lateral buckling (similar to what is observed for thin macroscopic membranes under tension). Finally, we also report on how the stress is transferred to the suspended specimen through the adhesive grips and determine the value of interfacial shear stress that is required for efficient axial loading in such a system

Elastic properties of graphene suspended on a polymer substrate by e-beam exposure

A method for fabricating multiple free-standing structures on the same sheet of graphene is demonstrated. Mechanically exfoliated mono- and bilayer graphene sheets were sandwiched between two layers of polymethyl-methacrylate. Suspended areas were defined by e-beam exposure allowing precise control over their shape and position. Mechanical characterization of suspended graphene sheets was performed by nanoindentation with an atomic force microscopy tip. The obtained built-in tensions of 12 nN are significantly lower than those in suspended graphene exfoliated on an SiO2 substrate, and therefore permit access to the intrinsic properties of this material system

Fully inkjet-printed two-dimensional material field-effect heterojunctions for wearable and textile electronics.

Fully printed wearable electronics based on two-dimensional (2D) material heterojunction structures also known as heterostructures, such as field-effect transistors, require robust and reproducible printed multi-layer stacks consisting of active channel, dielectric and conductive contact layers. Solution processing of graphite and other layered materials provides low-cost inks enabling printed electronic devices, for example by inkjet printing. However, the limited quality of the 2D-material inks, the complexity of the layered arrangement, and the lack of a dielectric 2D-material ink able to operate at room temperature, under strain and after several washing cycles has impeded the fabrication of electronic devices on textile with fully printed 2D heterostructures. Here we demonstrate fully inkjet-printed 2D-material active heterostructures with graphene and hexagonal-boron nitride (h-BN) inks, and use them to fabricate all inkjet-printed flexible and washable field-effect transistors on textile, reaching a field-effect mobility of ~91 cm2 V-1 s-1, at low voltage (<5 V). This enables fully inkjet-printed electronic circuits, such as reprogrammable volatile memory cells, complementary inverters and OR logic gates

Ultra-scaled MoS 2 transistors and circuits fabricated without nanolithography

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Ultra-low contact resistance in graphene devices at the Dirac point

Contact resistance is one of the main factors limiting performance of short-channel graphene field-effect transistors (GFETs), preventing their use in low-voltage applications. Here we investigated the contact resistance between graphene grown by chemical vapor deposition (CVD) and different metals, and found that etching holes in graphene below the contacts consistently reduced the contact resistance, down to 23 Omega . mu m with Au contacts. This low contact resistance was obtained at the Dirac point of graphene, in contrast to previous studies where the lowest contact resistance was obtained at the highest carrier density in graphene (here 200 Omega . mu m was obtained under such conditions). The 'holey' Au contacts were implemented in GFETs which exhibited an average transconductance of 940 S m(-1) at a drain bias of only 0.8 V and gate length of 500 nm, which out-perform GFETs with conventional Au contacts

Chiral transport of hot carriers in graphene in the quantum Hall regime

Photocurrent (PC) measurements can reveal the relaxation dynamics of photo-excited hot carriers beyond the linear response of conventional transport experiments, a regime important for carrier multiplication. In graphene subject to a magnetic field, PC measurements are able to probe the existence of Landau levels with different edge chiralities which is exclusive to relativistic electron systems. Here, we report the accurate measurement of PC in graphene in the quantum Hall regime. Prominent PC oscillations as a function of gate voltage on samples' edges are observed. These oscillation amplitudes form an envelope which depends on the strength of the magnetic field, as does the PCs' power dependence and their saturation behavior. We explain these experimental observations through a model using optical Bloch equations, incorporating relaxations through acoustic-, optical- phonons and Coulomb interactions. The simulated PC agrees with our experimental results, leading to a unified understanding of the chiral PC in graphene at various magnetic field strengths, and providing hints for the occurrence of a sizable carrier multiplication.Comment: 14 pages, 13 figure

Graphene-Si CMOS oscillators

Graphene field-effect transistors (GFETs) offer a possibility of exploiting unique physical properties of graphene in realizing novel electronic circuits. However, graphene circuits often lack the voltage swing and switchability of Si complementary metal-oxide-semiconductor (CMOS) circuits, which are the main building block of modern electronics. Here we introduce graphene in Si CMOS circuits to exploit favorable electronic properties of both technologies and realize a new class of simple oscillators using only a GFET, Si CMOS D latch, and timing RC circuit. The operation of the two types of realized oscillators is based on the ambipolarity of graphene, i.e., the symmetry of the transfer curve of GFETs around the Dirac point. The ambipolarity of graphene also allowed to turn the oscillators into pulse-width modulators (with a duty cycle ratio ∼1 : 4) and voltage-controlled oscillators (with a frequency ratio ∼1 : 8) without any circuit modifications. The oscillation frequency was in the range from 4 kHz to 4 MHz and limited only by the external circuit connections, rather than components themselves. The demonstrated graphene-Si CMOS hybrid circuits pave the way to the more widespread adoption of graphene in electronics